Digital logic circuits must sometimes coordinate operations across a synchronization boundary between two different clock domains operating at different clock speeds. In particular, a first-in-first-out (FIFO) memory is sometimes used to transfer data, commands and/or other information between the two different clock domains. Data is stored into the FIFO memory in a “write” clock domain at a write clock speed and read from the FIFO memory in a “read” clock domain at a read clock speed.
A FIFO memory write pointer, typically a register, is maintained in the write clock domain to point to the FIFO memory location in which data can be stored into the FIFO memory. A FIFO memory read pointer, also typically a register, is maintained in the read clock domain to point to the FIFO memory location from which data can be read from the FIFO memory. The FIFO memory read pointer and the FIFO memory write pointer are compared to each other to generate status information for the FIFO memory. Typically, the status information includes an “empty” signal, which indicates that all FIFO memory locations are empty, or no valid data is present (ss). A “full” (No room for additional information) signal indicates that all FIFO memory locations are full, or contain valid data. The empty signal is used to determine whether valid (ss)data can currently be read from the FIFO memory. The full signal is used to determine whether new (ss)data can currently be added to the FIFO memory.
Using the full and empty signals, a synchronization mechanism is implemented in the FIFO memory to prevent “overrun” and “underrun” conditions when writing to and reading from the FIFO memory. An overrun condition occurs when data is added to a FIFO memory location and overwrites previous data that has not yet been read from that FIFO memory location. An underrun condition occurs when data is read from a FIFO memory location before valid data has been stored into that FIFO memory location. The FIFO memory operations are typically synchronized by passing “handshaking” signals between the write clock domain and the read clock domain to request, acknowledge and reject data operations on the FIFO memory.
Pointer management and handshaking are complex functions that may be difficult to accomplish using standard cells. Moreover, handshaking can introduce latency, slowing data translation. There is therefore a need for an asynchronous FIFO design that can be made from standard cells, and that is consequently easily scalable between processes, and that simplifies pointer management.